Plasma Engine  2.0
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NEONVec4u_inl.h
1#pragma once
2
3PL_ALWAYS_INLINE plSimdVec4u::plSimdVec4u()
4{
5 PL_CHECK_SIMD_ALIGNMENT(this);
6
7#if PL_ENABLED(PL_MATH_CHECK_FOR_NAN)
8 m_v = vmovq_n_u32(0xCDCDCDCD);
9#endif
10}
11
12PL_ALWAYS_INLINE plSimdVec4u::plSimdVec4u(plUInt32 xyzw)
13{
14 PL_CHECK_SIMD_ALIGNMENT(this);
15
16 m_v = vmovq_n_u32(xyzw);
17}
18
19PL_ALWAYS_INLINE plSimdVec4u::plSimdVec4u(plUInt32 x, plUInt32 y, plUInt32 z, plUInt32 w)
20{
21 PL_CHECK_SIMD_ALIGNMENT(this);
22
23 alignas(16) plUInt32 values[4] = {x, y, z, w};
24 m_v = vld1q_u32(values);
25}
26
27PL_ALWAYS_INLINE plSimdVec4u::plSimdVec4u(plInternal::QuadUInt v)
28{
29 m_v = v;
30}
31
32PL_ALWAYS_INLINE void plSimdVec4u::Set(plUInt32 xyzw)
33{
34 m_v = vmovq_n_u32(xyzw);
35}
36
37PL_ALWAYS_INLINE void plSimdVec4u::Set(plUInt32 x, plUInt32 y, plUInt32 z, plUInt32 w)
38{
39 alignas(16) plUInt32 values[4] = {x, y, z, w};
40 m_v = vld1q_u32(values);
41}
42
43PL_ALWAYS_INLINE void plSimdVec4u::SetZero()
44{
45 m_v = vmovq_n_u32(0);
46}
47
48// needs to be implemented here because of include dependencies
49PL_ALWAYS_INLINE plSimdVec4i::plSimdVec4i(const plSimdVec4u& u)
50 : m_v(u.m_v)
51{
52}
53
54PL_ALWAYS_INLINE plSimdVec4u::plSimdVec4u(const plSimdVec4i& i)
55 : m_v(i.m_v)
56{
57}
58
59PL_ALWAYS_INLINE plSimdVec4f plSimdVec4u::ToFloat() const
60{
61 return vcvtq_f32_u32(m_v);
62}
63
64// static
65PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::Truncate(const plSimdVec4f& f)
66{
67 return vcvtq_u32_f32(f.m_v);
68}
69
70template <int N>
71PL_ALWAYS_INLINE plUInt32 plSimdVec4u::GetComponent() const
72{
73 return vgetq_lane_u32(m_v, N);
74}
75
76PL_ALWAYS_INLINE plUInt32 plSimdVec4u::x() const
77{
78 return GetComponent<0>();
79}
80
81PL_ALWAYS_INLINE plUInt32 plSimdVec4u::y() const
82{
83 return GetComponent<1>();
84}
85
86PL_ALWAYS_INLINE plUInt32 plSimdVec4u::z() const
87{
88 return GetComponent<2>();
89}
90
91PL_ALWAYS_INLINE plUInt32 plSimdVec4u::w() const
92{
93 return GetComponent<3>();
94}
95
96template <plSwizzle::Enum s>
97PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::Get() const
98{
99 return __builtin_shufflevector(m_v, m_v, PL_TO_SHUFFLE(s));
100}
101
102PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator+(const plSimdVec4u& v) const
103{
104 return vaddq_u32(m_v, v.m_v);
105}
106
107PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator-(const plSimdVec4u& v) const
108{
109 return vsubq_u32(m_v, v.m_v);
110}
111
112PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::CompMul(const plSimdVec4u& v) const
113{
114 return vmulq_u32(m_v, v.m_v);
115}
116
117PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator|(const plSimdVec4u& v) const
118{
119 return vorrq_u32(m_v, v.m_v);
120}
121
122PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator&(const plSimdVec4u& v) const
123{
124 return vandq_u32(m_v, v.m_v);
125}
126
127PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator^(const plSimdVec4u& v) const
128{
129 return veorq_u32(m_v, v.m_v);
130}
131
132PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator~() const
133{
134 return vmvnq_u32(m_v);
135}
136
137PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator<<(plUInt32 uiShift) const
138{
139 return vshlq_u32(m_v, vmovq_n_u32(uiShift));
140}
141
142PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::operator>>(plUInt32 uiShift) const
143{
144 return vshlq_u32(m_v, vmovq_n_u32(-uiShift));
145}
146
147PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator+=(const plSimdVec4u& v)
148{
149 m_v = vaddq_u32(m_v, v.m_v);
150 return *this;
151}
152
153PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator-=(const plSimdVec4u& v)
154{
155 m_v = vsubq_u32(m_v, v.m_v);
156 return *this;
157}
158
159PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator|=(const plSimdVec4u& v)
160{
161 m_v = vorrq_u32(m_v, v.m_v);
162 return *this;
163}
164
165PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator&=(const plSimdVec4u& v)
166{
167 m_v = vandq_u32(m_v, v.m_v);
168 return *this;
169}
170
171PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator^=(const plSimdVec4u& v)
172{
173 m_v = veorq_u32(m_v, v.m_v);
174 return *this;
175}
176
177PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator<<=(plUInt32 uiShift)
178{
179 m_v = vshlq_u32(m_v, vmovq_n_u32(uiShift));
180 return *this;
181}
182
183PL_ALWAYS_INLINE plSimdVec4u& plSimdVec4u::operator>>=(plUInt32 uiShift)
184{
185 m_v = vshlq_u32(m_v, vmovq_n_u32(-uiShift));
186 return *this;
187}
188
189PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::CompMin(const plSimdVec4u& v) const
190{
191 return vminq_u32(m_v, v.m_v);
192}
193
194PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::CompMax(const plSimdVec4u& v) const
195{
196 return vmaxq_u32(m_v, v.m_v);
197}
198
199PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator==(const plSimdVec4u& v) const
200{
201 return vceqq_u32(m_v, v.m_v);
202}
203
204PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator!=(const plSimdVec4u& v) const
205{
206 return vmvnq_u32(vceqq_u32(m_v, v.m_v));
207}
208
209PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator<=(const plSimdVec4u& v) const
210{
211 return vcleq_u32(m_v, v.m_v);
212}
213
214PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator<(const plSimdVec4u& v) const
215{
216 return vcltq_u32(m_v, v.m_v);
217}
218
219PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator>=(const plSimdVec4u& v) const
220{
221 return vcgeq_u32(m_v, v.m_v);
222}
223
224PL_ALWAYS_INLINE plSimdVec4b plSimdVec4u::operator>(const plSimdVec4u& v) const
225{
226 return vcgtq_u32(m_v, v.m_v);
227}
228
229// static
230PL_ALWAYS_INLINE plSimdVec4u plSimdVec4u::MakeZero()
231{
232 return vmovq_n_u32(0);
233}
234
235// not needed atm
236#if 0
237void plSimdVec4u::Transpose(plSimdVec4u& v0, plSimdVec4u& v1, plSimdVec4u& v2, plSimdVec4u& v3)
238{
239 uint32x4x2_t P0 = vzipq_u32(v0.m_v, v2.m_v);
240 uint32x4x2_t P1 = vzipq_u32(v1.m_v, v3.m_v);
241
242 uint32x4x2_t T0 = vzipq_u32(P0.val[0], P1.val[0]);
243 uint32x4x2_t T1 = vzipq_u32(P0.val[1], P1.val[1]);
244
245 v0.m_v = T0.val[0];
246 v1.m_v = T0.val[1];
247 v2.m_v = T1.val[0];
248 v3.m_v = T1.val[1];
249}
250#endif
Definition SimdVec4b.h:7
A 4-component SIMD vector class.
Definition SimdVec4f.h:8
A SIMD 4-component vector class of signed 32b integers.
Definition SimdVec4i.h:9
A SIMD 4-component vector class of unsigned 32b integers.
Definition SimdVec4u.h:7
static plSimdVec4u MakeZero()
Creates an plSimdVec4u that is initialized to zero.
Definition FPUVec4u_inl.h:313
A 4-component vector class.
Definition Vec4.h:9